Robrecht Belis; Romain Baudson, Elsyca.
Electroplating is used to deposit copper on PCB traces and within vias or through-holes. The resulting layer thickness depends on several factors, starting with the PCB design. Since the active surface—the regions exposed to plating—varies across the panel, thickness distribution is rarely uniform. Via filling adds further complexity. To achieve a fully filled, void-free via, specialized baths are required to promote bottom-up copper growth. As filling progresses, the active surface changes: initially including via walls and bottom, but reducing to the bottom area once the via closes. This shift alters process conditions over time and must be accounted for, especially in HDI boards with high via counts. This presentation will examine these challenges and show how simulation supports accurate prediction of copper thickness.