During the last decade, the electrochemical deposition of copper for multilevel interconnections has become accepted for mainstream silicon chip manufacturing. The tiny, sub-micron-sized interconnect structures that make up the chip circuitry involve new challenges for electroplating. These spaces must be filled with copper from the bottom up, to avoid creating voids in the lines and vias. The deposited film thickness uniformity across the wafer surface also must be controlled within 3 percent (one sigma) or less. Furthermore, the entire process must be performed at deposition rates that are economical to chipmakers in production lines.

The copper damascene interconnect application is the most prominent example of this type of process. In this process, the variations in current density over the wafer and also over time pose significant challenges in wafer plating. Elsyca has developed an enabling plating solution Elsyca IntelliTool that dynamically and intelligently addresses those issues. That technology also can be used during the copper deposition process at the packaging step.

Processes such as solder bump plating for flip-chip or controlled-collapse-chip-connection processes, redistribution of I/O pads, and related processes are also gaining use in the semiconductor and related industries. The important factors are typically

• thickness uniformity,
• deposition rate,
• and alloy composition control if alloys are being deposited.

Also for these applications, the Elsyca technology brings significant improvements when compared with other existing approaches.